ULtimate Integration on Silicon
17-19 March 2010, Glasgow, Scotland
Chairman: Dr. Scott Roy, University of Glasgow
Programme
| Wednesday 17th March | ||
| 12:00 | Registration (outside the Senate Room) | |
| Nanosil Visionary Workshop: High Mobility nMOS Substrates: Strained Si, Ge or III-V? | ||
| Venue: Room 408, Rankine Building, University of Glasgow | ||
| 14:00 | E. Simoen | Opening address |
| 14:10 | A. Asenov, University of Glasgow, UK | Modelling perspective of future n-channel high-mobility transistors |
| 14:50 | A. Dimoulas, Demokritos, Greece | The DUALLOGIC route to high-mobility n-channel devices |
| 15:30 | Coffee Break | |
| 15:50 | M. Meuris, IMEC, Belgium | The challenges of integrating III-V nMOS in next generation CMOS circuits |
| 16:30 | C. Le Royer, CEA-LETI, Minatec, France | Opportunities and challenges of the GeOI platform for future CMOS |
| 17:10 | Panel Discussion | |
| 17:55 | Closing Address | |
| 18:00 | Buses to Civic Reception at Glasgow City Chambers leaving from outside main gate. | |
| Thursday 18th March | ||
| Venue: Senate Room, University of Glasgow | ||
| Si MOS Technology | ||
| 09:00 | S. Datta | III-V compound MOSFET and TFET devices |
| 09:40 | S.F. Feste, J. Knoch, D. Buca, Q.T. Zhao, T. Schäpers and S. Mantl | Effective mass and I-V characterization of biaxially tensile strained SOI MOSFETs |
| 10:00 | J. El Husseini, J. Gyani, F. Martinez, M. Valenza, B. Ramadout, G.N. Lu, J.-P. Carrere and F. Roy | DC and low frequency noise characterisation of Multi gate N-MOSFET in a bulk technology by integrating polysilicon-filled trenches |
| 10:20 | S. Makovejev, S. Olsen, M. Dehan and J.-P. Raskin | Self-Heating Effect Characterisation in SOI FinFETs |
| 10:40 | Coffee and Posters | |
| 11:10 | M. Braccioli, A. Scholten, G. Curatola, E. Sangiorgi and C. Fiegna | AC and DC numerical simulation of Self–Heating Effects in FinFETs |
| 11:30 | M. Rodrigues, J.A. Martino, N. Collaert, E. Simoen and C. Claeys | Channel backscattering coefficient impact on FinFET devices with uniaxial/biaxial strain engineering |
| 11:50 | M. Poljak, V. Jovanović and T. Suligoj | Orientation-Dependent Electron Mobility Behavior with Downscaling of Fin-Width in Double- and Triple-Gate SOI FinFETs |
| 12:10 | E. Simoen, S. Put, P. Leroux, M. Van Uffelen, M. Jurczak and C. Claeys | Low-frequency noise analysis of γ-irradiated p-channel bulk MuGFETs |
| 12:30 | Lunch | |
| 13:30 | Poster Session | |
| Alternative Materials | ||
| 14:30 | I.G. Thayne, W. Jansen, X. Li, O. Ignatova, D.S. Macintyre, S. Thom and R. Droopad | Scaling of Flatband Mode III-V MOSFETs with a GaO/GaGdO gate dielectric stack and an In0.3GaAs channel |
| 14:50 | Q. Rafhay, R. Clerc, J. Coignus, G. Pananakakis and G. Ghibaudo | Dark Space, Quantum Capacitance and Inversion Capacitance in Si, Ge, GaAs and In0.53Ga0.47As nMOS Capacitors |
| 15:10 | L. Lattanzio, L. De Michielis, G. A. Salvatore, D. Bouvet, K. Boucart and A. M. Ionescu | Ferroelectric Tunnel FET with a SiO2/Al2O3/P(VDF-TrFE) gate stack |
| 15:30 | Coffee and Posters | |
| Variability & Circuits | ||
| 16:00 | P. Poliakov, P. Blomme, M. Miranda Corbalan, A. Anchlia, P. Dobrovolny, L. Brusamarello, M. Stucchi, J. Van Houdt and W. Dehaene. | Impact of Line Edge Roughness on Cell-to-Cell Coupling Variability in NAND Flash Arrays |
| 16:20 | D. Dideban, B. Cheng, N. Moezi, N. A. Kamsani, C. Millar, S. Roy and A. Asenov | Impact of Input Slew Rate on Statistical Timing and Power Dissipation Variability in nanoCMOS |
| 16:40 | E. Baravelli, L. Marchi and N. Speciale | Physical insight and Monte Carlo statistical analysis of Work-Function variability in FinFETs based on 2D slice composition |
| 17:00 | N. A. Kamsani, B. Cheng, C. Millar, N. Moezi, X. Wang, S. Roy and A. Asenov | Impact of Slew Rate Definition on the Accuracy of nanoCMOS Inverter Timing Simulations |
| 17:20 | End of 1st Day | |
| 20:00 | Conference Dinner at Òran Mór (see map) | |
| Friday 19th March | ||
| Venue: Senate Room, University of Glasgow | ||
| Simulation | ||
| 09:00 | K. Banerjee | Carbon based active and passive devices |
| 09:40 | I. Imperiale, R. Grassi, A. Gnudi, S. Reggiani, E. Gnani and G. Baccarani | Full-Quantum Calculations of Low-Field Channel Mobility in Graphene Nanoribbon FETs Including Acoustic Phonon Scattering and Edge Roughness Effects |
| 10:00 | V. Gudmundssona, P. Palestrib, P.-E. Hellströma, L. Selmib and M. Östling | Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs |
| 10:20 | P. Toniutti, M. De Michielis, P. Palestri, F. Driussi, D. Esseni and L. Selmi | Understanding the mobility reduction in MOSFETs featuring high-κ dielectrics |
| 10:40 | Z. Stanojević, O. Baumgartner, V. Sverdlov and H. Kosina | Subband Structure of Silicon Nanowires from the Hensel-Hasegawa-Nakayama Model |
| 11:00 | Coffee | |
| 11:30 | L. Silvestri, S. Reggiani, A. Gnudi, E. Gnani and G. Baccarani | Mobility Model for Electrons and Holes in FinFETs with High-κ Stacks, Metal Gate and Stress |
| 11:50 | A. García-Loureiro, M. Aldegunde, N. Seoane, K. Kalna and A. Asenov | Impact of Random Dopant Fluctuations on a Tri-Gate MOSFET |
| 12:10 | I. Moore, C. Millar, S. Roy and A. Asenov | Integrating Drift-Diffusion and Brownian Simulations for Sensory Applications |
| 12:30 | Lunch | |
| High-k & Memory | ||
| 13:30 | S.M. Thomas, M. J. Prest, T.E.Whall, C.S. Beer, D.R. Leadley and E.H.C. Parker, J.R. Watling, R.J.P. Lander and G. Vellianitis | Low temperature effective mobility measurements and modelling of high-κ gated Si n-MOS and p-MOS devices |
| 13:50 | E. Durğun Özben, J. M. J. Lopes, M. Roeckerath, A. Nichau, R. Luptak, S. Lenk, A. Besmehn, B. Ghyselen, Q.-T. Zhao, J. Schubert and S. Mantl | High mobility strained SOI MOSFETs with LaScO3/TiN gate stacks fabricated with a replacement gate process |
| 14:10 | K.-H. Park, M. Bawedin, J.-H. Lee, Y.-H. Bae, K.-I. Na and S. Cristoloveanu | A New Fully Depleted Double-Gate MSDRAM Cell with Added Nonvolatile Functionality |
| 14:30 | A. Arreghini, A. Suhane, G. Van den Bosch, L. Breuil, K. De Meyer, M. Jurczak and J. Van Houdt | Investigation on the temperature dependence of the dielectric constant of high-k materials for Non Volatile-Memory applications |
| 14:50 | Coffee | |
| Nanowires | ||
| 15:20 | K. E. Moselund, H. Ghoneim, H. Schmid, M. Björk, S. Karg, D. Webb, M. Tschudy, R. Beyeler and H. Riel | Diffusion doping of n-type and p-type VLS-grown silicon nanowire devices |
| 15:40 | C. Sandow, C. Urban, Q.-T. Zhao and S. Mantl | Silicon and Strained Silicon Nanowire Array Tunnel FETs |
| 16:00 | M.K. Md Arshad, J.-P. Raskin, V. Kilchytska, D. Flandre, O. Faynot, P. Scheiblin and F. Andrieu | Improved DIBL in Ultra Thin Body SOI MOSFETs with Ultra Thin Buried Oxide and Inverted Substrate |
| 16:20 | End of Conference | |
| Posters | ||
| P1 | M. Fathipour, S. M. Ebrahimi and Z. Ahangari | Design of a Novel Low Power Resonant Suspended Gate MOSFET with Metal Source-Drain |
| P2 | M. Kainlauri, M. Prunnila and J. Ahopelto, J. Kivioja, P. Laaksonen and M. Linder | Silicon-Protein Biointerface by Directed Self-Assembly |
| P3 | V. Beiu and W. Ibrahim | NAND Multiplexing Down to Nuts and Bolts |
| P4 | B. Benbakhti, K. Kalna, X. Wang, B. Cheng and A. Asenov | Impact of Raised Source/Drain in the In53Ga47As Channel Implant-Free Quantum-Well Transistor |
| P5 | A. Boubaker, N. Sghaier A. Souifi and A. Kalboussi | Simulation and Analysis of the Multi Tunnel Junction Memory Cell and the Hybrid MTJ/Ring Memory Using SIMON Simulator. |
| P6 | Y.-C. Chang, J.-T. Lin, Y.-C. Eng, C.-H. Chen, K.-U. Lu, C.-H. Tai and Y.-H. Fan | Block Oxide Length (Lbo) Effects in a bMOS Transistor |
| P7 | P.-O. Chapuis, M. Prunnila, A. Shchepetov, S. Laakso, J. Ahopelto and C.M. Sotomayor Torres | Phonon-based limitations of nanoelectronic devices: a setup design for phonon confinement studies |
| P8 | M. Cheralathan, A. Cerdeira and B. Iñiguez | Compact potential and current model for long-channel doped cylindrical surrounding-gate MOSFETs |
| P9 | S. Flachowsky, R. Illgen, T. Herrmann, T. Baldauf, A. Wei, J. Höntschel, W. Klix, R. Stenzel and M. Horstmann | Stress Memorization Technique for n-MOSFETs: Where is the Stress Memorized? |
| P10 | H. Ghanatian, F. Karimi, M. Tahermaram and M. Fathipour | Improvement of self-heating effect in nano-scale FinFET |
| P11 | J. Gyani, F. Martinez, S. Soliveres, M. Valenza, C. Le Royer, E. Augendre and L. Clavelier | Impact of Process Options on Low Frequency Noise in Germanium-on-Insulator (GeOI) high-K & Metal Gate pMOSFETs |
| P12 | F. Hong, B. Cheng and D. Cumming | Mismatch Modeling for a 35nm Differential Amplifier with Impact of Variability |
| P13 | N. M. Idris, A. R. Brown, J. R. Watling and A. Asenov | Simulation Study of Workfunction Variability in MOSFETs with Polycrystalline Metal Gates |
| P14 | F. Irrera, P. Lorenzi, R. Rao, R. Simoncini, G. Ghidini, H.D.B. Gottlob and M. Schmidt | Advanced Characterization of Metal/High-k Interface |
| P15 | C. Kampen, A. Burenkov, J. Lorenz and H. Ryssel | FD SOI MOSFET Compact Modeling Including Process Variations |
| P16 | S. Kiamehr, A.R. Ahmadi Mehr and A. Afzali Kusha | A Block-Based SSTA Method Considering Within-die Variation |
| P17 | D. Kirsten, D.M. Nuernbergk | Evaluation of Low Leakage Currents using a Floating Gate Transistor |
| P18 | P.-H. Lin, J.-T. Lin and Y.-C. Eng | An Improved Self-Aligned Double-Gate MOSFET Device with Source/Drain Tie |
| P19 | G. Lucovsky, L. Miotti, K Paz Bastos, C. Adamo and D.G. Schlom | Spectroscopic detection of spin-polarized bands and hopping-induced mixed valency in GdSc1-xTixO3 peroskites: x= 0.18 and 0.25: a novel approach to current controlled ferromagnetism in future generations pf multi-function Si device chips |
| P20 | G. Lucovsky, L. Miotti and K.B. Chung | Spectroscopic Studies Of Band Edge Bonding And Defect States In Transition Metal Gate Dielectrics: X-Ray Spectroscopy And Charge Transfer Multiplet Theory |
| P21 | S.N. Mozaffari, A. Afzali-Kusha | Gate-level statistical power analysis with considering the impact of process variation |
| P22 | J.L. Padilla and F. Gamiz | Barrier lowering implementation in SB-MOSFETs on SOI substrates |
| P23 | N. Peyvas, M.A. Malakoutian, M. Fathipour, V. Fathipour, M. Moradinasab and M.M. Allameh | Effects of a Buried Oxide Region on the Breakdown Voltage of Power LDMOS |
| P24 | C. Sampedro, F. Gamiz , A. Godoy , R. Valiny and A. Garcia-Loureiro | Channel Length impact on Velocity Overshoot in UTB-DGSOI |
| P25 | E. San Andrés, M. A. Pampillón, M. L. Lucía, P. Feijoo, A. del Prado and M. Toledano-Luque. | Growth of gadolinium oxide by thermal oxidation of thin metallic gadolinium layers |
| P26 | M. Saremi, B. Ebrahimi and A. Afzali-Kusha | Ground Plane SOI MOSFET Based SRAM with Consideration of Process Variation |
| P27 | M. Schwarz, A. Kloes and B. Iñíguez | 2D Closed-Form Model for the Source/Drain Orthogonal Electric Field in Lightly Doped Schottky Barrier Double-Gate MOSFET |
| P28 | L. Tan, M. M. A. Hakim, S. Connor, A. Bousquet, W. Redman-White, P. Ashburn and S. Hall | Compact Model Extraction Issues of a CMOS Compatible Vertical MOSFET |
| P29 | K. Wu, R.B. Brown and H.-H. Cheng | Schottky Barrier Quantum Well Resonant Tunneling Transistor (SBQWRTT) a.k.a. H Transistor |
| P30 | M. Younespour , M. Vadizadeh, M. Tahermaram, A. Anis and G. Abaeiani | A Employing a Novel Constant Gate Voltage for Reduction of Gate Induced Drain leakage Current in Nanoscale Silicon on Insulator MOSFETs |
| P31 | Y. Nakajima, Y. Watanabe, T. Hanajiri, T. Toyabe, and T. Sugano | Impact of Local Stress Near SOI/BOX interface on high-density trap states in SIMOX wafers |